The present invention relates to a vertical transistor, and more specifically, to an asymmetrical vertical transistor.
A field effect transistor (FET) is a three-terminal device that includes a source, drain, and gate. Generally, a FET is fabricated with the source and drain formed on the same lateral level such that current flow, which is controlled by the gate in the channel region between the source and drain regions, is horizontal. In the efforts to scale complementary metal-oxide semiconductor (CMOS) technologies to 5 nanometers and beyond, vertical FETs (VFETs) have been pursued. In a VFET, the source and drain are not on the same lateral plane but, instead, on the same vertical plane. As a result, current flow in the channel region is vertical rather than horizontal.